IPC Performance Report Shows Ultra-low Latencies Of 660 Nanoseconds

Experts agree that in the future CPU scaling will go out, not up. Clock cycles seem to have plateaued around 3 Gigahertz, and while five years ago people got excited about dual-core machines, today the major commodity CPU manufacturers deliver 4, 6 and 8-core processors and system vendors link these CPUs together in multi-socket servers, as Cisco does in their UCS line.

Our Ultra Messaging customers – financial players like exchanges and investment banks – are always interested in gaining every possible performance advantage in the ultra competitive world of high-frequency electronic trading.

In order to take advantage of this highly horizontal movement in CPU architecture, Informatica’s 29West Ultra Messaging has integrated a new mode of transporting data from application to application via shared memory. Called IPC (Inter-Process Communication), this transport mechanism routes data messages among applications running on the same physical machine.

Our latest performance report, based on recent testing by Cisco and 29West, highlights the kind of next-generation performance that is achievable when using world-class enterprise software and hardware. As a result of these tests, we are able to show latency measurement and througput:

Sub-microsecond average latencies, as low as 660 nanoseconds

Maximum fan-out throughput of 21.1 million messages per second

Nearly perfect linear horizontal scaling to multiple CPU cores

The report includes testing methodology, along with full descriptions of the technology stack under test, hardware and software.

The full report is available free here.

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